Patent · US8941236B2 · B2 · US
Using collapse limiter structures between elements to reduce solder bump bridging
- (11) Publication number
- US8941236B2
- (21) Application number
- 13/631,713
- (22) Filing date
- 2012-09-28
- (30) Priority date
- 2012-09-28
- (43) Publication date
- 2015-01-27
- (45) Date of grant
- 2015-01-27
- (51) IPC
- H01L 21/50; H01L 23/498; H01L 23/48
- (52) CPC
- H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 90/701, 72/0198, 72/072, 72/07202, 72/07227, 72/07236, 72/241, 72/252, 90/724
- (73) Assignee
- Intel Corp
- (72) Inventors
- Ameya LIMAYE; Richard J. Harries; Sandeep B. Sane
- (54) Title
- Using collapse limiter structures between elements to reduce solder bump bridging
- (57) Abstract
Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.
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Claims (16)
- An electronic assembly, comprising: a first element having a first surface; a second element having a second surface; electrical connections between the first and the second elements formed by heating solder bumps; and a plurality of collapse limiter structures coupled to at least one of the first and the second surfaces, wherein the plurality of collapse limiter structures are dispersed in an array of the electrical connections, wherein the array includes at least three electrical connections in a first direction and at least four electrical connections in a second direction, and wherein in the array, a plurality of the collapse limiter structures are positioned between different pairs of electrical connections in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation.
- The electronic assembly of claim 1, wherein at least one of the collapse limiter structures comprises: a first end of the collapse limiter structure connected to the first surface; and a second flexible end of the collapse limiter structure that is substantially curved such that when the curved second flexible end contacts the second surface the collapse limiter structure flexes.
- The electronic assembly of claim 2, wherein the first end comprises two ends separated by a space to form a u-shaped collapse limiter structure.
- The electronic assembly of claim 1, wherein at least one of the collapse limiter structures comprises a spring shape.
- The electronic assembly of claim 1, wherein the first element comprises a package substrate in which an integrated circuit die is mounted, and wherein the second element comprises a printed circuit board on which the package substrate is mounted.
- The of claim 1, wherein the first element comprises an integrated circuit die and wherein the second element comprises a package substrate on which the integrated circuit die is mounted.
- An electronic assembly, comprising: a package substrate having a first surface and having a semiconductor die mounted on a second surface; a printed circuit board having a third surface; electrical connections between the first surface and the third surface formed by heating solder bumps; and a plurality of collapse limiter structures coupled to at least one of the first and the third surfaces, wherein the collapse limiter structures are dispersed in an array of the electrical connections, wherein the array includes at least three electrical connections in a first direction and at least four electrical connections in a second direction, wherein at least one of the collapse limiter structures has a first end connected to the first surface and a second flexible end such that when the second flexible end contacts the second surface the collapse limiter structure flexes to allow for a flexible contact with the second surface at different collapse levels for the first surface, and wherein in the array, a plurality of the collapse limiter structures are positioned between different pairs of electrical connections in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation.
- The electronic assembly of claim 7, wherein the collapse limiter structure has a shape selected from the group consisting of: a spring shape, a cylindrical shape, and a u-shape.
- A method for forming an electronic assembly, comprising: forming solder bumps on a first surface of a first element; positioning a plurality of collapse limiter structures to be dispersed in an array of the solder bumps, wherein the array includes at least three electrical connections in a first direction and at least four electrical connections in a second direction, wherein in the array, the collapse limiter structures are positioned between different pairs of the solder bumps in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation; positioning the first element and a second element so that the solder bumps are between the first element and the second element; performing a heating operation to connect the solder bumps to a second surface of the second element to form electrical connections between the first and second surfaces, wherein the at the plurality of collapse limiter structures are coupled to at least one of the first surface and the second surface after the heating operation.
- The method of claim 9, further comprising: forming solder paste on the second surface opposite the solder bumps on the first surface, wherein the heating causes the solder bumps and the solder paste to melt to form the electrical connections.
- The method of claim 9, wherein at least one of the collapse limiter structures comprises a first end connected to the first surface and a second flexible end that is substantially curved such that when the curved second flexible end contacts the second surface the collapse limiter structure flexes.
- The method of claim 11, wherein the first end comprises two ends separated by a space to form a u-shaped collapse limiter structure.
- The method of claim 9, wherein at least one of the collapse limiter structures comprises a spring shape.
- The method of claim 9, wherein the first element comprises a package substrate in which an integrated circuit die is mounted, and wherein the second element comprises a printed circuit board on which the package substrate is mounted.
- The of method claim 9, wherein the first element comprises an integrated circuit die and wherein the second element comprises a package substrate on which the integrated circuit die is mounted.
- A method for forming an electronic assembly, comprising: forming solder bumps on a first surface of a package substrate including a semiconductor die at which at least two solder bumps will be located; positioning a plurality of collapse limiter structures on the first surface, wherein the plurality of collapse limiter structures are dispersed among an array of the solder bumps wherein the array includes at least three solder bumps in a first direction and at least four solder bumps in a second direction, and wherein in the array, a plurality of the collapse limiter structures are positioned between different pairs of the solder bumps in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation; forming solder paste on a second surface of a printed circuit board; positioning the package substrate and a printed circuit board so that the solder bumps are between the package substrate and the printed circuit board and at locations corresponding to locations of the solder past; performing a heating operation to have the solder bumps connect to the second surface of the printed circuit board to form electronic connections therebetween, wherein at least one of the collapse limiter structures has a first end connected to the first surface and a second flexible end such that when the second flexible end contacts the second surface during the heating the collapse limiter structure flexes to allow for a flexible contact with the second surface at different collapse levels for the first surface, and wherein the at least one collapse limiter structure is coupled to at least one of the first surface and the second surface after the heating operation.
Description
Integrated circuits may be formed on semiconductor wafers made from materials such as silicon. The semiconductor wafers are processed to form various electronic devices. The wafers are diced into semiconductor chips (a chip is also known as a die), which may then be attached to a package substrate using a variety of known methods.
The package substrate may be mounted on a printed circuit board using surface mount technology (SMT). In one known method for mounting a package substrate to a printed circuit board, the package substrate may have solder bumps which are electrically coupled to a surface of the package substrate. The solder bump contacts extend onto solder paste printed on contact pads of the printed circuit board, and are typically attached in a thermal reflow process. Electronic signals may be provided through the solder bump contacts to and from the package substrate, including the integrated circuits, and the printed circuit board.
The material of the package substrate typically does not provide a match with the material of the integrated circuit die with respect to the coefficient of thermal expansion. Thermal expansion mismatch can lead to undesirable stresses developing in the electronic assembly during processing procedures, in particular, during heating and cooling operations. Such stresses may cause the package substrate to warp.
Embodiments are described by way of example, with reference to the accompanying drawings, which are not drawn to scale, wherein:
Citations (22)
- US3871015A
- US4545610A
- US5598036A
- US5968670A
- US5950073A
- US6552425B1
- US6559527B2
- US6506681B2
- US6653730B2
- US6667548B2
- US6541305B2
- US6703697B2
- US6631078B2
- US6753613B2
- US6673697B2
- US20040109283A1
- US6849944B2
- US20050051906A1
- US20050067685A1
- US7160757B2
- US20110084375A1
- US20120020040A1
Record as JSON
{
"publication_number": "US8941236B2",
"country": "US",
"kind": "B2",
"title": "Using collapse limiter structures between elements to reduce solder bump bridging",
"abstract": "Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.",
"claims": [
"1. An electronic assembly, comprising: a first element having a first surface; a second element having a second surface; electrical connections between the first and the second elements formed by heating solder bumps; and a plurality of collapse limiter structures coupled to at least one of the first and the second surfaces, wherein the plurality of collapse limiter structures are dispersed in an array of the electrical connections, wherein the array includes at least three electrical connections in a first direction and at least four electrical connections in a second direction, and wherein in the array, a plurality of the collapse limiter structures are positioned between different pairs of electrical connections in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation.",
"2. The electronic assembly of claim 1, wherein at least one of the collapse limiter structures comprises: a first end of the collapse limiter structure connected to the first surface; and a second flexible end of the collapse limiter structure that is substantially curved such that when the curved second flexible end contacts the second surface the collapse limiter structure flexes.",
"3. The electronic assembly of claim 2, wherein the first end comprises two ends separated by a space to form a u-shaped collapse limiter structure.",
"4. The electronic assembly of claim 1, wherein at least one of the collapse limiter structures comprises a spring shape.",
"5. The electronic assembly of claim 1, wherein the first element comprises a package substrate in which an integrated circuit die is mounted, and wherein the second element comprises a printed circuit board on which the package substrate is mounted.",
"6. The of claim 1, wherein the first element comprises an integrated circuit die and wherein the second element comprises a package substrate on which the integrated circuit die is mounted.",
"7. An electronic assembly, comprising: a package substrate having a first surface and having a semiconductor die mounted on a second surface; a printed circuit board having a third surface; electrical connections between the first surface and the third surface formed by heating solder bumps; and a plurality of collapse limiter structures coupled to at least one of the first and the third surfaces, wherein the collapse limiter structures are dispersed in an array of the electrical connections, wherein the array includes at least three electrical connections in a first direction and at least four electrical connections in a second direction, wherein at least one of the collapse limiter structures has a first end connected to the first surface and a second flexible end such that when the second flexible end contacts the second surface the collapse limiter structure flexes to allow for a flexible contact with the second surface at different collapse levels for the first surface, and wherein in the array, a plurality of the collapse limiter structures are positioned between different pairs of electrical connections in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation.",
"8. The electronic assembly of claim 7, wherein the collapse limiter structure has a shape selected from the group consisting of: a spring shape, a cylindrical shape, and a u-shape.",
"9. A method for forming an electronic assembly, comprising: forming solder bumps on a first surface of a first element; positioning a plurality of collapse limiter structures to be dispersed in an array of the solder bumps, wherein the array includes at least three electrical connections in a first direction and at least four electrical connections in a second direction, wherein in the array, the collapse limiter structures are positioned between different pairs of the solder bumps in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation; positioning the first element and a second element so that the solder bumps are between the first element and the second element; performing a heating operation to connect the solder bumps to a second surface of the second element to form electrical connections between the first and second surfaces, wherein the at the plurality of collapse limiter structures are coupled to at least one of the first surface and the second surface after the heating operation.",
"10. The method of claim 9, further comprising: forming solder paste on the second surface opposite the solder bumps on the first surface, wherein the heating causes the solder bumps and the solder paste to melt to form the electrical connections.",
"11. The method of claim 9, wherein at least one of the collapse limiter structures comprises a first end connected to the first surface and a second flexible end that is substantially curved such that when the curved second flexible end contacts the second surface the collapse limiter structure flexes.",
"12. The method of claim 11, wherein the first end comprises two ends separated by a space to form a u-shaped collapse limiter structure.",
"13. The method of claim 9, wherein at least one of the collapse limiter structures comprises a spring shape.",
"14. The method of claim 9, wherein the first element comprises a package substrate in which an integrated circuit die is mounted, and wherein the second element comprises a printed circuit board on which the package substrate is mounted.",
"15. The of method claim 9, wherein the first element comprises an integrated circuit die and wherein the second element comprises a package substrate on which the integrated circuit die is mounted.",
"16. A method for forming an electronic assembly, comprising: forming solder bumps on a first surface of a package substrate including a semiconductor die at which at least two solder bumps will be located; positioning a plurality of collapse limiter structures on the first surface, wherein the plurality of collapse limiter structures are dispersed among an array of the solder bumps wherein the array includes at least three solder bumps in a first direction and at least four solder bumps in a second direction, and wherein in the array, a plurality of the collapse limiter structures are positioned between different pairs of the solder bumps in the first direction and the second direction wherein a length of the collapse limiter structures dispersed in the array between different pairs of electrical connections is less than a height of the electrical connections attached to the first surface before the heating operation; forming solder paste on a second surface of a printed circuit board; positioning the package substrate and a printed circuit board so that the solder bumps are between the package substrate and the printed circuit board and at locations corresponding to locations of the solder past; performing a heating operation to have the solder bumps connect to the second surface of the printed circuit board to form electronic connections therebetween, wherein at least one of the collapse limiter structures has a first end connected to the first surface and a second flexible end such that when the second flexible end contacts the second surface during the heating the collapse limiter structure flexes to allow for a flexible contact with the second surface at different collapse levels for the first surface, and wherein the at least one collapse limiter structure is coupled to at least one of the first surface and the second surface after the heating operation."
],
"description_excerpt": "Integrated circuits may be formed on semiconductor wafers made from materials such as silicon. The semiconductor wafers are processed to form various electronic devices. The wafers are diced into semiconductor chips (a chip is also known as a die), which may then be attached to a package substrate using a variety of known methods.\n\nThe package substrate may be mounted on a printed circuit board using surface mount technology (SMT). In one known method for mounting a package substrate to a printed circuit board, the package substrate may have solder bumps which are electrically coupled to a surface of the package substrate. The solder bump contacts extend onto solder paste printed on contact pads of the printed circuit board, and are typically attached in a thermal reflow process. Electronic signals may be provided through the solder bump contacts to and from the package substrate, including the integrated circuits, and the printed circuit board.\n\nThe material of the package substrate typically does not provide a match with the material of the integrated circuit die with respect to the coefficient of thermal expansion. Thermal expansion mismatch can lead to undesirable stresses developing in the electronic assembly during processing procedures, in particular, during heating and cooling operations. Such stresses may cause the package substrate to warp.\n\nEmbodiments are described by way of example, with reference to the accompanying drawings, which are not drawn to scale, wherein:",
"cpc": [
"H10W 90/701",
"H10W 72/0198",
"H10W 72/072",
"H10W 72/07202",
"H10W 72/07227",
"H10W 72/07236",
"H10W 72/241",
"H10W 72/252",
"H10W 90/724"
],
"ipc": [
"H01L 21/50",
"H01L 23/498",
"H01L 23/48"
],
"assignees": [
"Intel Corp"
],
"inventors": [
"Ameya LIMAYE",
"Richard J. Harries",
"Sandeep B. Sane"
],
"filing_date": "2012-09-28",
"publication_date": "2015-01-27",
"grant_date": "2015-01-27",
"priority_date": "2012-09-28",
"application_number": "US-201213631713-A",
"family_id": "50384402",
"cited_by_count": 3,
"citations": [
"US3871015A",
"US4545610A",
"US5598036A",
"US5968670A",
"US5950073A",
"US6552425B1",
"US6559527B2",
"US6506681B2",
"US6653730B2",
"US6667548B2",
"US6541305B2",
"US6703697B2",
"US6631078B2",
"US6753613B2",
"US6673697B2",
"US20040109283A1",
"US6849944B2",
"US20050051906A1",
"US20050067685A1",
"US7160757B2",
"US20110084375A1",
"US20120020040A1"
]
}
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