Method to manufacture dual damascene structures by utilizing short resist spacers

{
  "publication_number": "US6103616A",
  "country": "US",
  "kind": "A",
  "title": "Method to manufacture dual damascene structures by utilizing short resist spacers",
  "abstract": "A method of manufacturing semiconductor devices wherein a partially completed semiconductor device having a first and second layer of interlayer dielectric and a first and second etch stop layer has the second etch stop layer masked and etched with an etch pattern having dimensions of the trench structure to be formed in the second interlayer dielectric. The second layer dielectric and first etch stop layer are then masked and etched with an etch pattern having dimensions of the via structure to be formed in the first interlayer dielectric. The remaining portions of the photoresist is removed and exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric are then etched simultaneously. The via structure and trench structure are then simultaneously filled with a conductive material.",
  "claims": [
    "1. A method of manufacturing a semiconductor device, the method comprising: forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices; forming a first etch stop layer on a surface of the first layer of interlayer dielectic; forming a second layer of interlayer dielectric on a surface of the first etch stop layer; forming a second etch stop layer on a surface of the second layer of interlayer dielectric; forming a first layer of photoresist on a surface of the second etch stop layer; etching the first layer of photoresist down to the surface of the second etch stop layer with an etch pattern having dimensions of a trench structure that will be formed in the second layer of interlayer dielectric wherein a portion of the second layer of interlayer dielectric is exposed having dimensions of the trench structure; removing the first layer of photoresist; forming a second layer of photoresist on the surface of the second etch stop layer and the exposed portion of the second layer of interlayer dielectric; etching the second layer of photoresist down to the surface of the second layer of interlayer dielectric with an etch pattern having dimensions of a via structure to be formed in the first layer of interlayer dielectric; etching the second layer of interlayer dielectric down to the surface of the first etch stop layer exposing a region of the first etch stop layer having dimensions of the via structure to be formed in the first layer interlayer dielectric; etching the exposed portions of the first etch stop layer; removing the second layer of photoresist exposing portions of the second layer of interlayer dielectric; and etching the exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric down to the surface of the semiconductor substrate exposing a region of the semiconductor substrate having dimensions of the via structure to be formed.",
    "2. The method of claim 1 further comprising filling the via structure formed in the first layer of interlayer dielectric and the trench structure in the second layer of interlayer dielectric with a conductive material.",
    "3. The method of claim 2 wherein the conductive material is selected from the group consisting of aluminum, tungsten and copper.",
    "4. The method of claim 3 wherein the first etch stop layer is formed from a material selected from the group consisting of SiON and Si 3 N 4 and the second etch stop layer is formed from a material selected from the group consisting of SiON, Si 3 N 4 and TiN.",
    "5. The method of claim 4 wherein the first and second layers of interlayer dielectric are formed from a low dielectric constant material.",
    "6. The method of claim 5 wherein the first and second layers of interlayer dielectric are formed from silicon dioxide."
  ],
  "description_excerpt": "1. Field of the Invention\n\nThis invention relates generally to a method of manufacturing high density, high performance semiconductor devices that have dual damascene interconnects. More specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices that have dual damascene structures that are formed with a reduced number of masks.\n\n2. Discussion of the Related Art\n\nThe increased demand for higher performance semiconductor devices has required more complex process technologies and materials to be utilized in the manufacture of semiconductor integrated devices. One way to increase the performance of a semiconductor integrated device such as a microprocessor is to reduce the gate width of the field effect transistors in the device in order to achieve a high internal clock speed for the microprocessor. The reduced gate widths have increased the performance significantly, however, the interconnect structure of the microprocessor has proved to be a roadblock to further increase in performance. This is because as increased performance is required, more transistors require more wiring in the interconnect structure. The increased density of the wiring can result in a decrease in performance relating to RC delays. To counteract the degradation in performance due to the RC delays, additional layers, commonly referred to as metal layers, in which interconnects are formed are manufactured in the semiconductor device in order to separate the wiring in both the vertical and horizontal directions.",
  "cpc": [
    "H10W 20/087",
    "H10W 20/088"
  ],
  "ipc": [
    "H01L 21/768"
  ],
  "assignees": [
    "Advanced Micro Devices Inc"
  ],
  "inventors": [
    "Allen S. Yu",
    "Thomas C. Scholer",
    "Paul J. Steffan"
  ],
  "filing_date": "1998-08-19",
  "publication_date": "2000-08-15",
  "grant_date": "2000-08-15",
  "priority_date": "1998-08-19",
  "application_number": "US-13686798-A",
  "family_id": "22474746",
  "cited_by_count": 30,
  "citations": [
    "US5635423A",
    "US5741626A",
    "US6037664A",
    "US6037213A",
    "US5916823A"
  ]
}