Semiconductor device with conductive plugs

{
  "publication_number": "US6004839A",
  "country": "US",
  "kind": "A",
  "title": "Semiconductor device with conductive plugs",
  "abstract": "In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.",
  "claims": [
    "1. A method of manufacturing a semiconductor device comprising the steps of: forming on a substrate a CMOS section comprising an N-channel MOS transistor and a P-channel MOS transistor and a memory section comprising at least a transfer gate MOS transistor; forming a plurality of conductive plugs to penetrate a laminate insulating film, at least one of said plurality of conductive plugs being associated with, and connected to, one each of said MOS transistors in said CMOS section and said memory section, said laminate insulating film being comprised of a first insulating film and a second insulating film; forming a capacitor section on said laminate insulating film, said capacitor section being comprised of an upper electrode, a dielectric film and a lower electrode; forming a third insulating film on said laminate insulating film and said capacitor section; and forming a wiring pattern on said third insulating film to partially penetrate said second insulating film and connect to said plurality of conductive plugs.",
    "2. A method according to claim 1, wherein said step of forming a plurality of conductive plugs includes: forming said first insulating film on said substrate, said CMOS section and said memory section; forming said second insulating film on said first insulating film; forming contact holes to penetrate said first and second insulating films to said MOS transistors; and filling said contact holes with at least one conductive material.",
    "3. A method according to claim 2, wherein said step of filling said contact holes includes: forming a barrier film in said contact holes; and forming a heat resistant material film on said barrier film in said contact holes.",
    "4. A method according to claim 3, wherein said step forming a barrier film includes heating said barrier film to form a silicide layer.",
    "5. A method according to claim 1, wherein said step of forming a plurality of conductive plugs includes: forming said first insulating film on said substrate, said CMOS section and said memory section; forming first contact holes to penetrate said first insulating films to said MOS transistors; filling said first contact holes with at least one conductive material to form first contacts; forming said second insulating film on said first insulating film; forming second contact holes to penetrate said second insulating films to said first contacts; and filling said second contact holes with at least one conductive material.",
    "6. A method according to claim 5, wherein said step of filling said first contact holes includes: forming a barrier film in said first contact holes; and filling said contact holes with a heat resistant material film on said barrier film, and wherein said step of filling said second contact holes includes: forming a barrier film in said second contact holes; and filling said second contact holes with a heat resistant material film on said first contacts.",
    "7. A method according to claim 1, further comprising the steps of: forming said first insulating film on said substrate, said CMOS section and said memory section; forming a bit line wiring pattern on said first insulating film to penetrate said first insulating film to said transfer gate MOS transistor; and forming said second insulating film on said first insulating film to complete said laminate insulating film.",
    "8. A method according to claim 1, further comprising the steps of: forming said first insulating film on said substrate, said CMOS section and said memory section; etching said first insulating film to form a trench pattern and to form first contact holes to said MOS transistors, a part of said first contact holes being connected to said trench pattern; filling said trench pattern and first contact holes with a film composed of conductive heat resistant material; forming said second insulating film on said first insulating film; forming second contact holes to penetrate said second insulating films to remaining ones of said first contacts which are not connected to said trench pattern; and filling said second contact holes with a film composed of conductive heat resistant material to complete said plurality of conductive plugs.",
    "9. A method according to claim 8, wherein a part of said trench pattern which is filled said film composed of conductive heat resistant material at least one conductive material is a bit line connected to said transfer gate MOS transistor.",
    "10. A method according to claim 1, wherein said step of forming a capacitor section includes forming a capacitor section on said laminate insulating film such that said lower electrode is positioned on and connected to one of said plurality of conductive plugs.",
    "11. A method according to claim 1, wherein said step of forming a capacitor section includes forming said lower electrode, and wherein said step of forming said lower electrode includes: depositing first and second metal films on said laminate insulating film; and forming an oxidation resistant layer from said first metal film and crystallizing said second metal film.",
    "12. A method according to claim 1, wherein said of forming a capacitor section includes: forming a lower electrode conductive film on said laminate insulating film; forming a dielectric film on said lower electrode conductive film; forming a protective conductive film on said dielectric film; patterning said lower electrode conductive film, said dielectric film and said protective film; forming an upper electrode conductive film; and patterning said upper electrode film to form said upper electrode.",
    "13. A method according to claim 12, further comprising the step of depositing a hydrogen diffusion preventing conductive film, and where said patterning said upper electrode film includes patterning said hydrogen diffusion preventing conductive film at the same time as patterning said upper electrode film.",
    "14. A method of manufacturing a semiconductor device according to claim 1, wherein each of said plurality of conductive plugs have a height substantially equal to a greatest thickness of said laminate insulating film.",
    "15. A method of manufacturing a semiconductor device according to claim 1, wherein each of said plurality of conductive plugs have a first end closest to said substrate and a second end away from said substrate, and said second end of said conductive plugs is substantially coincident height as said top surface of said laminate insulating film.",
    "16. A method of manufacturing a semiconductor device according to claim 1, wherein said dielectric film includes a noble metal protecting film on a ferroelectric film.",
    "17. A method of manufacturing a semiconductor device according to claim 4, wherein said dielectric film is covered on an upper surface by a noble metal protecting film.",
    "18. A method of manufacturing a semiconductor device according to claim 4, wherein each of said plurality of conductive plugs have a first end closest to said substrate and a second end away from said substrate, and said second end of said conductive plugs is substantially coincident height as said top surface of said laminate insulating film.",
    "19. A method of manufacturing a semiconductor device according to claim 1, wherein each of said plurality of first conductive plugs comprises: a barrier film composed of a titanium silicide layer and a titanium nitride layer and a tungsten film."
  ],
  "description_excerpt": "This is a divisional of application Ser. No. 08/754,808 filed Nov. 21, 1996 pending Dec. 31, 1998.\n\n1. Field of the Invention\n\nThe present invention relates to a non-volatile semiconductor memory device which includes a dielectric film such as a ferroelectric thin film, and a method of manufacturing the same, and more particularly to a non-volatile semiconductor memory device using a heat-resistant metal and a method of manufacturing the same.\n\n2. Description of Related Art\n\nAs a non-volatile semiconductor memory devices there is a ferroelectric semiconductor memory device in which a ferroelectric thin film having a polarization hysteresis is used for a capacitor section. In recent years, the ferroelectric semiconductor memory device is also required to be manufactured with a high density. As a result, the ferroelectric semiconductor memory device has been developed such that a transistor, wiring and a capacitor section are manufactured in a small size and contact holes are manufactured with high aspect ratio.\n\nFIG. 1 is a circuit diagram illustrating a memory capacitor cell of a conventional ferroelectric semiconductor memory device using a ferroelectric thin film. The memory capacitor cell is composed of an NMOSFET as a transfer gate 1 and a ferroelectric capacitor 4. The ferroelectric thin film is provided between a charge storing electrode 2 and a plate electrode 3. The gate electrode of the NMOSFET 1 is connected to a word line 5. One of the diffusion layers of the NMOSFET is connected to a bit line 6 and the other diffusion layer is connected to the charge storing electrode 2 of the ferroelectric capacitor 4.",
  "cpc": [
    "H10W 20/01",
    "H10B 12/01",
    "H10B 12/033",
    "H10B 53/00",
    "H10B 53/30"
  ],
  "ipc": [
    "H01L 21/768",
    "H10B 12/00",
    "H10B 20/00"
  ],
  "assignees": [
    "NEC Corp"
  ],
  "inventors": [
    "Yoshihiro Hayashi",
    "Nobuhiro Tanabe",
    "Tsuneo Takeuchi",
    "Shinobu Saito"
  ],
  "filing_date": "1997-02-20",
  "publication_date": "1999-12-21",
  "grant_date": "1999-12-21",
  "priority_date": "1996-01-17",
  "application_number": "US-80411297-A",
  "family_id": "26339443",
  "cited_by_count": 60,
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}