ADPLL

{
  "id": "MLC-T-IND-006743",
  "term": "ADPLL",
  "field": "Industrial and trades",
  "definition": "All-Digital Phase-Locked Loop, an electronic circuit that synchronizes an output signal's phase and frequency with a reference input signal using entirely digital components. Unlike analog PLLs, ADPLLs offer advantages in terms of integration, programmability, and robustness against noise. They are commonly used in clock generation, frequency synthesis, and data recovery applications.",
  "subject": "Electrical engineering",
  "see_also": [
    "PLL",
    "DPLL"
  ],
  "references": [
    "A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency - National Central University (scholars.ncu.edu.tw)"
  ],
  "translations": {
    "de": "ADPLL",
    "es": "ADPLL",
    "fr": "ADPLL"
  },
  "url": "https://mlchart.com/terminology/industrial/adpll/"
}