MLchartDataset catalogue

Layout versus schematic

Term · Semiconductors · MLC-T-SEM-000193

A verification step in integrated circuit design that compares the physical layout of a circuit with its corresponding schematic diagram. This comparison identifies discrepancies between the intended design and its physical implementation, such as missing or extra transistors, incorrect connections, or shorts. LVS tools extract connectivity information from both the layout and the schematic to perform this check, typically reporting any mismatches to the designer.

Table 1. Record
IdentifierMLC-T-SEM-000193
FieldSemiconductors
SubjectDesign, EDA & Devices
AbbreviationLVS
Record as JSON 
{
  "id": "MLC-T-SEM-000193",
  "term": "Layout versus schematic",
  "field": "Semiconductors",
  "definition": "A verification step in integrated circuit design that compares the physical layout of a circuit with its corresponding schematic diagram. This comparison identifies discrepancies between the intended design and its physical implementation, such as missing or extra transistors, incorrect connections, or shorts. LVS tools extract connectivity information from both the layout and the schematic to perform this check, typically reporting any mismatches to the designer.",
  "abbreviation": "LVS",
  "subject": "Design, EDA & Devices",
  "url": "https://mlchart.com/terminology/semiconductors/layout-versus-schematic/"
}

Record 197 of 390 in Semiconductors terminology (MLC-0108). Request the full dataset.