MLchartDataset catalogue

Latch-up

Term · Semiconductors · MLC-T-SEM-000192

A condition in a complementary metal-oxide-semiconductor (CMOS) integrated circuit where a parasitic silicon-controlled rectifier (SCR) structure is inadvertently triggered, creating a low-resistance path between the power supply rails. This can lead to excessive current flow and potentially destructive failure of the device if not quickly mitigated. Latch-up is typically initiated by transient overvoltage conditions or by carriers injected into the substrate.

Table 1. Record
IdentifierMLC-T-SEM-000192
FieldSemiconductors
SubjectTest & Reliability
Record as JSON 
{
  "id": "MLC-T-SEM-000192",
  "term": "Latch-up",
  "field": "Semiconductors",
  "definition": "A condition in a complementary metal-oxide-semiconductor (CMOS) integrated circuit where a parasitic silicon-controlled rectifier (SCR) structure is inadvertently triggered, creating a low-resistance path between the power supply rails. This can lead to excessive current flow and potentially destructive failure of the device if not quickly mitigated. Latch-up is typically initiated by transient overvoltage conditions or by carriers injected into the substrate.",
  "subject": "Test & Reliability",
  "url": "https://mlchart.com/terminology/semiconductors/latch-up/"
}

Record 196 of 390 in Semiconductors terminology (MLC-0108). Request the full dataset.