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Patent · US11223014B2 · B2 · US

Semiconductor structures including liners comprising alucone and related methods

(11) Publication number
US11223014B2
(21) Application number
16/446,746
(22) Filing date
2019-06-20
(30) Priority date
2014-02-25
(43) Publication date
2022-01-11
(45) Date of grant
2022-01-11
(52) CPC
  • H10P Generic processes or apparatus for the manufacture or treatment of devices covered by class H10: 14/69391, 14/6339, 14/6548, 14/662, 14/683, 50/285, 50/71, 76/4085
  • H01L Electric elements: 21/02118, 21/02178, 21/0228, 21/02362, 21/0337, 27/1157, 27/11582, 27/2409, 27/2427, 27/249, 45/06, 45/065, 45/1233, 45/126, 45/141, 45/1608, 45/1675, 45/1691
  • H10B Electronic memory devices: 43/27, 43/35, 63/20, 63/24, 63/845
  • H10N Electric solid-state devices not otherwise provided for: 70/021, 70/063, 70/068, 70/231, 70/235, 70/826, 70/8413, 70/882
(73) Assignee
MICRON TECHNOLOGY INC
(54) Title
Semiconductor structures including liners comprising alucone and related methods
(57) Abstract

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

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Claims (18)

  1. A semiconductor device, comprising: stack structures overlying a material; and a liner on sidewalls of the stack structures, the liner comprising: a first portion comprising aluminum oxide in contact with the sidewalls of the stack structures; and a second portion comprising alucone contacting the first portion, the second portion further comprising at least one of silicon atoms or nitrogen atoms.
  2. The semiconductor device of claim 1, wherein the liner comprises a gradient of alucone and aluminum oxide.
  3. The semiconductor device of claim 1, wherein the second portion comprises from about 10 atomic percent to about 20 atomic percent silicon.
  4. The semiconductor device of claim 1, wherein the liner comprises a ratio of aluminum oxide to alucone of from about 1:1 to about 1:10.
  5. The semiconductor device of claim 1, wherein the stack structures comprise an electrode and a switching material adjacent the electrode.
  6. The semiconductor device of claim 1, wherein the liner further comprises a third portion between the first portion and the second portion, the third portion comprising a greater amount of alucone than the first portion.
  7. The semiconductor device of claim 1, wherein the stack structures comprise an electrode between a switching material and a phase change material.
  8. The semiconductor device of claim 1, wherein the liner has a thickness ranging from about 5 Å to about 30 Å.
  9. The semiconductor device of claim 1, wherein the stack structures comprise alternating conductive materials and dielectric materials.
  10. A semiconductor device, comprising: a base material; 3D-NAND memory structures comprising stack structures vertically overlying the base material, each stack structure comprising alternating dielectric materials and conductive materials, the alternating dielectric materials vertically spaced from each other by the conductive materials; and a liner comprising alucone on sidewalls of the stack structures, the liner comprising a gradient of aluminum oxide and alucone, a concentration of alucone increasing from about zero percent at the sidewalls of each stack structure to about one-hundred percent at an outer surface of the liner distal from the sidewalls of the respective stack structure.
  11. The semiconductor device of claim 10, wherein the stack structures comprises a control gate material.
  12. The semiconductor device of claim 10, wherein the liner has a thickness between about 5 Å and about 30 Å.
  13. The semiconductor device of claim 10, wherein the alternating dielectric materials comprise silicon dioxide.
  14. The semiconductor device of claim 10, wherein the alternating conductive materials comprise tungsten.
  15. The semiconductor device of claim 10, wherein the liner further comprises from about 10 atomic percent to about 20 atomic percent of at least one of silicon and nitrogen.
  16. A method of forming a semiconductor device, the method comprising: forming stack structures overlying a base material; and forming a liner on sidewalls of the stack structures, forming the liner comprising: forming a first portion comprising aluminum oxide in contact with the sidewalls of the stack structures; and forming a second portion comprising alucone contacting the first portion, the second portion further comprising at least one of silicon atoms and nitrogen atoms.
  17. The method of claim 16, wherein forming a second portion comprising alucone contacting the first portion comprises forming the second portion to exhibit a gradient of alucone and aluminum oxide.
  18. The method of claim 16, wherein forming stack structures overlying a base material comprises forming stack structures comprising alternating dielectric materials and conductive materials overlying the base material.

Citations (100)

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Record as JSON
{
  "publication_number": "US11223014B2",
  "country": "US",
  "kind": "B2",
  "title": "Semiconductor structures including liners comprising alucone and related methods",
  "abstract": "A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.",
  "claims": [
    "1. A semiconductor device, comprising: stack structures overlying a material; and a liner on sidewalls of the stack structures, the liner comprising: a first portion comprising aluminum oxide in contact with the sidewalls of the stack structures; and a second portion comprising alucone contacting the first portion, the second portion further comprising at least one of silicon atoms or nitrogen atoms.",
    "2. The semiconductor device of claim 1, wherein the liner comprises a gradient of alucone and aluminum oxide.",
    "3. The semiconductor device of claim 1, wherein the second portion comprises from about 10 atomic percent to about 20 atomic percent silicon.",
    "4. The semiconductor device of claim 1, wherein the liner comprises a ratio of aluminum oxide to alucone of from about 1:1 to about 1:10.",
    "5. The semiconductor device of claim 1, wherein the stack structures comprise an electrode and a switching material adjacent the electrode.",
    "6. The semiconductor device of claim 1, wherein the liner further comprises a third portion between the first portion and the second portion, the third portion comprising a greater amount of alucone than the first portion.",
    "7. The semiconductor device of claim 1, wherein the stack structures comprise an electrode between a switching material and a phase change material.",
    "8. The semiconductor device of claim 1, wherein the liner has a thickness ranging from about 5 Å to about 30 Å.",
    "9. The semiconductor device of claim 1, wherein the stack structures comprise alternating conductive materials and dielectric materials.",
    "10. A semiconductor device, comprising: a base material; 3D-NAND memory structures comprising stack structures vertically overlying the base material, each stack structure comprising alternating dielectric materials and conductive materials, the alternating dielectric materials vertically spaced from each other by the conductive materials; and a liner comprising alucone on sidewalls of the stack structures, the liner comprising a gradient of aluminum oxide and alucone, a concentration of alucone increasing from about zero percent at the sidewalls of each stack structure to about one-hundred percent at an outer surface of the liner distal from the sidewalls of the respective stack structure.",
    "11. The semiconductor device of claim 10, wherein the stack structures comprises a control gate material.",
    "12. The semiconductor device of claim 10, wherein the liner has a thickness between about 5 Å and about 30 Å.",
    "13. The semiconductor device of claim 10, wherein the alternating dielectric materials comprise silicon dioxide.",
    "14. The semiconductor device of claim 10, wherein the alternating conductive materials comprise tungsten.",
    "15. The semiconductor device of claim 10, wherein the liner further comprises from about 10 atomic percent to about 20 atomic percent of at least one of silicon and nitrogen.",
    "16. A method of forming a semiconductor device, the method comprising: forming stack structures overlying a base material; and forming a liner on sidewalls of the stack structures, forming the liner comprising: forming a first portion comprising aluminum oxide in contact with the sidewalls of the stack structures; and forming a second portion comprising alucone contacting the first portion, the second portion further comprising at least one of silicon atoms and nitrogen atoms.",
    "17. The method of claim 16, wherein forming a second portion comprising alucone contacting the first portion comprises forming the second portion to exhibit a gradient of alucone and aluminum oxide.",
    "18. The method of claim 16, wherein forming stack structures overlying a base material comprises forming stack structures comprising alternating dielectric materials and conductive materials overlying the base material."
  ],
  "cpc": [
    "H10P 14/69391",
    "H01L 21/02118",
    "H01L 21/02178",
    "H01L 21/0228",
    "H01L 21/02362",
    "H01L 21/0337",
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    "H10B 43/27",
    "H10B 43/35",
    "H10B 63/20",
    "H10B 63/24",
    "H10B 63/845",
    "H10N 70/021",
    "H10N 70/063",
    "H10N 70/068",
    "H10N 70/231",
    "H10N 70/235",
    "H10N 70/826",
    "H10N 70/8413",
    "H10N 70/882",
    "H10P 14/6339",
    "H10P 14/6548",
    "H10P 14/662",
    "H10P 14/683",
    "H10P 50/285",
    "H10P 50/71",
    "H10P 76/4085"
  ],
  "assignees": [
    "MICRON TECHNOLOGY INC"
  ],
  "filing_date": "2019-06-20",
  "publication_date": "2022-01-11",
  "grant_date": "2022-01-11",
  "priority_date": "2014-02-25",
  "application_number": "US-201916446746-A",
  "family_id": "68097393",
  "citations": [
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  ]
}

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