Patent · US9548332B2 · B2 · US

Method of forming a micro LED device with self-aligned metallization stack

(11) Publication number

US9548332B2

(21) Application number

13/458,932

(22) Filing date

2012-04-27

(30) Priority date

2012-04-27

(43) Publication date

2017-01-17

(45) Date of grant

2017-01-17

(51) IPC

H01L 33/62; H01L 33/60; H01L 23/00; H01L 27/15

(52) CPC

H10H Inorganic light-emitting semiconductor devices having potential barriers: 29/142, 20/00, 20/01, 20/018, 20/80, 20/81, 20/819, 20/835, 20/84
H01L Semiconductor devices; electric solid state devices not otherwise provided for: 2224/7598, 2224/95, 24/75, 24/83, 24/95, 25/0753, 27/156, 2924/00, 2924/12041, 2924/12042, 33/0079, 33/0095, 33/20, 33/405, 33/44
H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 72/0198, 72/0711, 72/073, 90/00

(73) Assignee

Apple Inc

(72) Inventors

Hsin-Hua Hu; Andreas Bibl

(54) Title

Method of forming a micro LED device with self-aligned metallization stack

(57) Abstract

A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, a patterned sacrificial layer is utilized to form a self-aligned metallization stack and is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes.

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Claims (26)

A method of forming a micro LED array comprising: forming a plurality of laterally separate self-aligned metallization stacks within a corresponding plurality of openings in a patterned sacrificial layer formed on a p-n diode layer; bonding a first substrate stack including the plurality of laterally separate self-aligned metallization stacks, the patterned sacrificial layer, and the p-n diode layer to a second substrate with a bonding layer; etching through the p-n diode layer to form a plurality of micro p-n diodes over the plurality of separate metallization stacks, and exposing the patterned sacrificial layer laterally between the plurality of separate metallization stacks; and removing the patterned sacrificial layer.
The method of claim 1, wherein forming the plurality of laterally separate self-aligned metallization stacks within the corresponding plurality of openings in the patterned sacrificial layer formed on the p-n diode layer comprises: depositing a sacrificial layer over the p-n diode layer; forming a patterned mask layer over the sacrificial layer, the patterned mask layer including the plurality of openings exposing the sacrificial layer; selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer; depositing a metallization stack layer over the patterned mask layer and p-n diode layer; lifting off the patterned mask layer to leave behind the plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer.
The method of claim 1, wherein etching through the p-n diode layer comprises plasma etching.
The method of claim 1, wherein the plurality of self-aligned metallization stacks include an electrode layer and a barrier layer.
The method of claim 4, wherein the barrier layer covers an elevated surface and sidewalls of the electrode layer.
The method of claim 5, wherein the electrode layer is reflective.
The method of claim 6, wherein the electrode layer comprises a material selected from the group consisting of silver and nickel.
The method of claim 5, wherein forming the plurality of laterally separate self-aligned metallization stacks comprises depositing the barrier layer at a higher power than the electrode layer, or at a lower pressure than the electrode layer.
The method of claim 1, wherein the patterned sacrificial layer is a non-metallic layer.
The method of claim 9, wherein the patterned sacrificial layer comprises SiO 2.
The method of claim 4, wherein the patterned sacrificial layer is thicker than the plurality of laterally separate self-aligned metallization stacks.
The method of claim 11, wherein the patterned sacrificial layer is approximately twice as thick as the plurality of laterally separate self-aligned metallization stacks.
The method of claim 4, wherein forming the plurality of self-aligned metallization stacks comprises a technique selected from the group consisting of evaporation and sputtering.
The method of claim 1, further comprising depositing a conformal dielectric barrier layer on side surfaces and a portion of a bottom surface of each of the plurality of micro p-n diodes.
The method of claim 1, wherein the bonding layer has a liquidus temperature of approximately 350° C. or lower.
The method of claim 15, wherein the bonding layer has a liquidus temperature of approximately 200° C. or lower.
The method of claim 15, wherein the bonding layer comprises indium.
The method of claim 15, wherein bonding the first substrate stack to the second substrate with the bonding layer comprises bonding a first bonding layer on the first substrate stack with a second bonding layer on the second substrate.
The method of claim 18, wherein bonding comprises alloy bonding or fusion bonding the first and second bonding layers.
A method of forming a micro LED array comprising: depositing a sacrificial layer over a p-n diode layer; and forming a patterned mask layer over the sacrificial layer, the patterned mask layer including a plurality of openings exposing the sacrificial layer; forming a patterned sacrificial layer, wherein forming the patterned sacrificial layer includes selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer; depositing a metallization stack layer over the patterned mask layer and p-n diode layer; lifting off the patterned mask layer to leave behind a plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer, wherein the patterned sacrificial layer is thicker than the plurality of metallization stacks; bonding a first substrate stack including the plurality of metallization stacks, the patterned sacrificial layer and the p-n diode layer to a second substrate with a bonding layer; plasma etching through the p-n diode layer to form a plurality of micro p-n diodes over the plurality of separate metallization stacks, and exposing the patterned sacrificial layer laterally between the plurality of separate metallization stacks; and removing the patterned sacrificial layer.
A method of forming a micro LED array comprising: depositing a sacrificial layer over a p-n diode layer formed on a growth substrate; and forming a patterned mask layer over the sacrificial layer, the patterned mask layer including a plurality of openings exposing the sacrificial layer; forming a patterned sacrificial layer, wherein forming the patterned sacrificial layer includes selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer; depositing a metallization stack layer over the patterned mask layer and p-n diode layer; lifting off the patterned mask layer to leave behind a plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer, wherein the patterned sacrificial layer is thicker than the plurality of metallization stacks.
The method of claim 21, wherein the plurality of self-aligned metallization stacks each include an electrode layer and a barrier layer covering an elevated surface and sidewalls of the electrode layer.
The method of claim 22, wherein the electrode layer is reflective.
The method of claim 23, wherein the electrode layer comprises a material selected from the group consisting of silver and nickel.
The method of claim 22, wherein forming the plurality of laterally separate self-aligned metallization stacks comprises depositing the barrier layer at a higher power than the electrode layer, or at a lower pressure than the electrode layer.
The method of claim 22, further comprising: bonding a first substrate stack including the plurality of metallization stacks, the p-n diode layer, and the growth substrate to a second substrate with a bonding layer; and removing the growth substrate.

Description

Field

The present invention relates to micro devices. More particularly embodiments of the present invention relate to a method of forming an array of micro devices such as light emitting diodes (LEDs) and transferring to a different substrate.

vBackground Information

Light emitting diodes (LEDs) based upon gallium nitride (GaN) are expected to be used in future high-efficiency lighting applications, replacing incandescent and fluorescent lighting lamps. Current GaN-based LED devices are prepared by heteroepitaxial growth techniques on foreign substrate materials. A typical wafer level LED device structure may include a lower n-doped GaN layer formed over a sapphire growth substrate, a single quantum well (SQW) or multiple quantum well (MWQ), and an upper p-doped GaN layer.

In one implementation, the wafer level LED device structure is patterned into an array of mesas on the sapphire growth substrate by etching through the upper p-doped GaN layer, quantum well layer, and into the n-doped GaN layer. An upper p-electrode is formed on the top p-doped GaN surfaces of the array of mesas, and an n-electrode is formed on a portion of the n-doped GaN layer which is in contact with the array of mesas. The mesa LED devices remain on the sapphire growth substrate in the final product.

In another implementation, the wafer level LED device structure is transferred from the growth substrate to an acceptor substrate such as silicon, which has the advantage of being more easily diced to form individual chips than a GaN/sapphire composite structure.

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Record as JSON

{
  "publication_number": "US9548332B2",
  "country": "US",
  "kind": "B2",
  "title": "Method of forming a micro LED device with self-aligned metallization stack",
  "abstract": "A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, a patterned sacrificial layer is utilized to form a self-aligned metallization stack and is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes.",
  "claims": [
    "1. A method of forming a micro LED array comprising: forming a plurality of laterally separate self-aligned metallization stacks within a corresponding plurality of openings in a patterned sacrificial layer formed on a p-n diode layer; bonding a first substrate stack including the plurality of laterally separate self-aligned metallization stacks, the patterned sacrificial layer, and the p-n diode layer to a second substrate with a bonding layer; etching through the p-n diode layer to form a plurality of micro p-n diodes over the plurality of separate metallization stacks, and exposing the patterned sacrificial layer laterally between the plurality of separate metallization stacks; and removing the patterned sacrificial layer.",
    "2. The method of claim 1, wherein forming the plurality of laterally separate self-aligned metallization stacks within the corresponding plurality of openings in the patterned sacrificial layer formed on the p-n diode layer comprises: depositing a sacrificial layer over the p-n diode layer; forming a patterned mask layer over the sacrificial layer, the patterned mask layer including the plurality of openings exposing the sacrificial layer; selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer; depositing a metallization stack layer over the patterned mask layer and p-n diode layer; lifting off the patterned mask layer to leave behind the plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer.",
    "3. The method of claim 1, wherein etching through the p-n diode layer comprises plasma etching.",
    "4. The method of claim 1, wherein the plurality of self-aligned metallization stacks include an electrode layer and a barrier layer.",
    "5. The method of claim 4, wherein the barrier layer covers an elevated surface and sidewalls of the electrode layer.",
    "6. The method of claim 5, wherein the electrode layer is reflective.",
    "7. The method of claim 6, wherein the electrode layer comprises a material selected from the group consisting of silver and nickel.",
    "8. The method of claim 5, wherein forming the plurality of laterally separate self-aligned metallization stacks comprises depositing the barrier layer at a higher power than the electrode layer, or at a lower pressure than the electrode layer.",
    "9. The method of claim 1, wherein the patterned sacrificial layer is a non-metallic layer.",
    "10. The method of claim 9, wherein the patterned sacrificial layer comprises SiO 2.",
    "11. The method of claim 4, wherein the patterned sacrificial layer is thicker than the plurality of laterally separate self-aligned metallization stacks.",
    "12. The method of claim 11, wherein the patterned sacrificial layer is approximately twice as thick as the plurality of laterally separate self-aligned metallization stacks.",
    "13. The method of claim 4, wherein forming the plurality of self-aligned metallization stacks comprises a technique selected from the group consisting of evaporation and sputtering.",
    "14. The method of claim 1, further comprising depositing a conformal dielectric barrier layer on side surfaces and a portion of a bottom surface of each of the plurality of micro p-n diodes.",
    "15. The method of claim 1, wherein the bonding layer has a liquidus temperature of approximately 350° C. or lower.",
    "16. The method of claim 15, wherein the bonding layer has a liquidus temperature of approximately 200° C. or lower.",
    "17. The method of claim 15, wherein the bonding layer comprises indium.",
    "18. The method of claim 15, wherein bonding the first substrate stack to the second substrate with the bonding layer comprises bonding a first bonding layer on the first substrate stack with a second bonding layer on the second substrate.",
    "19. The method of claim 18, wherein bonding comprises alloy bonding or fusion bonding the first and second bonding layers.",
    "20. A method of forming a micro LED array comprising: depositing a sacrificial layer over a p-n diode layer; and forming a patterned mask layer over the sacrificial layer, the patterned mask layer including a plurality of openings exposing the sacrificial layer; forming a patterned sacrificial layer, wherein forming the patterned sacrificial layer includes selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer; depositing a metallization stack layer over the patterned mask layer and p-n diode layer; lifting off the patterned mask layer to leave behind a plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer, wherein the patterned sacrificial layer is thicker than the plurality of metallization stacks; bonding a first substrate stack including the plurality of metallization stacks, the patterned sacrificial layer and the p-n diode layer to a second substrate with a bonding layer; plasma etching through the p-n diode layer to form a plurality of micro p-n diodes over the plurality of separate metallization stacks, and exposing the patterned sacrificial layer laterally between the plurality of separate metallization stacks; and removing the patterned sacrificial layer.",
    "21. A method of forming a micro LED array comprising: depositing a sacrificial layer over a p-n diode layer formed on a growth substrate; and forming a patterned mask layer over the sacrificial layer, the patterned mask layer including a plurality of openings exposing the sacrificial layer; forming a patterned sacrificial layer, wherein forming the patterned sacrificial layer includes selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer; depositing a metallization stack layer over the patterned mask layer and p-n diode layer; lifting off the patterned mask layer to leave behind a plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer, wherein the patterned sacrificial layer is thicker than the plurality of metallization stacks.",
    "22. The method of claim 21, wherein the plurality of self-aligned metallization stacks each include an electrode layer and a barrier layer covering an elevated surface and sidewalls of the electrode layer.",
    "23. The method of claim 22, wherein the electrode layer is reflective.",
    "24. The method of claim 23, wherein the electrode layer comprises a material selected from the group consisting of silver and nickel.",
    "25. The method of claim 22, wherein forming the plurality of laterally separate self-aligned metallization stacks comprises depositing the barrier layer at a higher power than the electrode layer, or at a lower pressure than the electrode layer.",
    "26. The method of claim 22, further comprising: bonding a first substrate stack including the plurality of metallization stacks, the p-n diode layer, and the growth substrate to a second substrate with a bonding layer; and removing the growth substrate."
  ],
  "description_excerpt": "Field\n\nThe present invention relates to micro devices. More particularly embodiments of the present invention relate to a method of forming an array of micro devices such as light emitting diodes (LEDs) and transferring to a different substrate.\n\nvBackground Information\n\nLight emitting diodes (LEDs) based upon gallium nitride (GaN) are expected to be used in future high-efficiency lighting applications, replacing incandescent and fluorescent lighting lamps. Current GaN-based LED devices are prepared by heteroepitaxial growth techniques on foreign substrate materials. A typical wafer level LED device structure may include a lower n-doped GaN layer formed over a sapphire growth substrate, a single quantum well (SQW) or multiple quantum well (MWQ), and an upper p-doped GaN layer.\n\nIn one implementation, the wafer level LED device structure is patterned into an array of mesas on the sapphire growth substrate by etching through the upper p-doped GaN layer, quantum well layer, and into the n-doped GaN layer. An upper p-electrode is formed on the top p-doped GaN surfaces of the array of mesas, and an n-electrode is formed on a portion of the n-doped GaN layer which is in contact with the array of mesas. The mesa LED devices remain on the sapphire growth substrate in the final product.\n\nIn another implementation, the wafer level LED device structure is transferred from the growth substrate to an acceptor substrate such as silicon, which has the advantage of being more easily diced to form individual chips than a GaN/sapphire composite structure.",
  "cpc": [
    "H10H 29/142",
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    "H01L 2224/95",
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    "H01L 25/0753",
    "H01L 27/156",
    "H01L 2924/00",
    "H01L 2924/12041",
    "H01L 2924/12042",
    "H01L 33/0079",
    "H01L 33/0095",
    "H01L 33/20",
    "H01L 33/405",
    "H01L 33/44",
    "H10H 20/00",
    "H10H 20/01",
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    "H10H 20/80",
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  "ipc": [
    "H01L 33/62",
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  ],
  "assignees": [
    "Apple Inc"
  ],
  "inventors": [
    "Hsin-Hua Hu",
    "Andreas Bibl"
  ],
  "filing_date": "2012-04-27",
  "publication_date": "2017-01-17",
  "grant_date": "2017-01-17",
  "priority_date": "2012-04-27",
  "application_number": "US-201213458932-A",
  "family_id": "49476523",
  "cited_by_count": 26,
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Record 4,355 of 8,000 in Patents full text (MLC-0201). Request the full dataset.