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Register-transfer level

Term · Semiconductors · MLC-T-SEM-000284

A level of abstraction for modeling a digital circuit by defining its behavior in terms of data transfers between storage elements (registers) and the logical operations performed on that data. This design methodology, known as Register-transfer level (RTL), focuses on the synchronous flow of signals between registers on each clock cycle, ignoring the specific gate-level details. Designs at this level are described using a hardware description language like Verilog or VHDL before synthesis.

Table 1. Record
IdentifierMLC-T-SEM-000284
FieldSemiconductors
SubjectDesign, EDA & Devices
AbbreviationRTL
Record as JSON 
{
  "id": "MLC-T-SEM-000284",
  "term": "Register-transfer level",
  "field": "Semiconductors",
  "definition": "A level of abstraction for modeling a digital circuit by defining its behavior in terms of data transfers between storage elements (registers) and the logical operations performed on that data. This design methodology, known as Register-transfer level (RTL), focuses on the synchronous flow of signals between registers on each clock cycle, ignoring the specific gate-level details. Designs at this level are described using a hardware description language like Verilog or VHDL before synthesis.",
  "abbreviation": "RTL",
  "subject": "Design, EDA & Devices",
  "url": "https://mlchart.com/terminology/semiconductors/register-transfer-level/"
}

Record 294 of 390 in Semiconductors terminology (MLC-0108). Request the full dataset.