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Wafer-level packaging

Term · Semiconductors · MLC-T-SEM-000350

A packaging technology where the packaging and testing of integrated circuits are performed while the devices are still in wafer form. This approach processes all chips on a wafer simultaneously, rather than individually after dicing. Wafer level packaging reduces manufacturing costs and package size compared to traditional single-chip packaging methods.

Table 1. Record
IdentifierMLC-T-SEM-000350
FieldSemiconductors
SubjectPackaging & ATMP
AbbreviationWLP
Record as JSON 
{
  "id": "MLC-T-SEM-000350",
  "term": "Wafer-level packaging",
  "field": "Semiconductors",
  "definition": "A packaging technology where the packaging and testing of integrated circuits are performed while the devices are still in wafer form. This approach processes all chips on a wafer simultaneously, rather than individually after dicing. Wafer level packaging reduces manufacturing costs and package size compared to traditional single-chip packaging methods.",
  "abbreviation": "WLP",
  "subject": "Packaging & ATMP",
  "url": "https://mlchart.com/terminology/semiconductors/wafer-level-packaging/"
}

Record 373 of 390 in Semiconductors terminology (MLC-0108). Request the full dataset.