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Scan chain

Term · Semiconductors · MLC-T-SEM-000292

A design-for-test (DFT) technique where flip-flops within a semiconductor integrated circuit are reconfigured into a serial shift register during test mode. This allows for the sequential loading of test patterns and unloading of test responses, enabling thorough testing of internal logic states. Scan chains are a standard method for detecting manufacturing defects in complex digital circuits.

Table 1. Record
IdentifierMLC-T-SEM-000292
FieldSemiconductors
SubjectTest & Reliability
Record as JSON 
{
  "id": "MLC-T-SEM-000292",
  "term": "Scan chain",
  "field": "Semiconductors",
  "definition": "A design-for-test (DFT) technique where flip-flops within a semiconductor integrated circuit are reconfigured into a serial shift register during test mode. This allows for the sequential loading of test patterns and unloading of test responses, enabling thorough testing of internal logic states. Scan chains are a standard method for detecting manufacturing defects in complex digital circuits.",
  "subject": "Test & Reliability",
  "url": "https://mlchart.com/terminology/semiconductors/scan-chain/"
}

Record 302 of 390 in Semiconductors terminology (MLC-0108). Request the full dataset.