Patent · US9343448B2 · B2 · US
Active matrix emissive micro LED display
- (11) Publication number
- US9343448B2
- (21) Application number
- 14/860,185
- (22) Filing date
- 2015-09-21
- (30) Priority date
- 2012-12-10
- (43) Publication date
- 2016-05-17
- (45) Date of grant
- 2016-05-17
- (51) IPC
- H01L 25/16; H01L 33/06; H01L 33/38; H01L 33/42; H01L 33/54; H01L 33/62
- (52) CPC
- H10W Generic packages, interconnections, connectors or other constructional details of devices covered by class H10: 72/0198, 70/093, 70/099, 70/60, 72/0711, 72/07141, 72/07178, 72/073, 72/07336, 72/352, 72/874, 90/00
- H01L Semiconductor devices; electric solid state devices not otherwise provided for: 25/167, 33/06, 33/38, 33/42, 33/54, 33/62
- H10D Inorganic electric semiconductor devices: 86/40, 86/60
- H10H Inorganic light-emitting semiconductor devices having potential barriers: 20/812, 20/831, 20/833, 20/853, 20/857
- (73) Assignee
- LuxVue Technology Corp
- (72) Inventors
- Kapil V. Sakariya; Andreas Bibl; Hsin-Hua Hu
- (54) Title
- Active matrix emissive micro LED display
- (57) Abstract
A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.
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Claims (20)
- A display panel comprising: a lower conductive layer including a ground line; a planarization layer over the lower conductive layer; an opening in the planarization layer; a patterned top conductive layer over the planarization layer, wherein the patterned top conductive layer includes: an array of bottom electrodes; and a ground contact within the opening in the planarization layer and in electrical contact with the ground line; a corresponding plurality of light emitting diodes (LEDs) bonded to the array of bottom electrodes; and one or more top electrode layers on and in electrical contact with the plurality of LEDs and the ground contact.
- The display panel of claim 1, wherein each LED comprises an inorganic semiconductor-based p-n diode.
- The display panel of claim 2, wherein each LED is a vertical LED with a maximum width of 1 μm-100 μm.
- The display panel of claim 3, wherein each bottom electrode is independently addressable.
- The display panel of claim 4, wherein each LED device has a maximum width of 1 μm-20 μm.
- The display panel of claim 3, wherein the one or more top electrode layers includes a single top electrode layer on and in electrical contact with the plurality of LEDs and the ground contact.
- The display panel of claim 3, wherein the one or more top electrode layers includes a plurality of top electrode layers.
- The display panel of claim 7, wherein each top electrode layer spans over a plurality of rows of LEDs.
- The display panel of claim 7, wherein each top electrode layer spans over a single row of LEDs.
- The display panel of claim 3, further comprising a patterned bank layer including an array of bank openings over the planarization layer, wherein each LED is within a corresponding bank opening.
- The display panel of claim 10, further comprising a passivation layer spanning sidewalls of the array of LEDs within the array of bank openings, wherein the passivation layer does not completely cover a top conductive contact of each LED.
- The display panel of claim 11, wherein the one or more top electrode layers spans across the passivation layer.
- The display panel of calm 11, wherein the passivation layer is transparent to the visible wavelength spectrum.
- The display panel of claim 11, wherein the patterned bank layer is opaque.
- The display panel of claim 11, wherein the passivation layer spans a quantum well structure for each LED.
- The display panel of claim 11, wherein the opening is formed in the patterned bank layer and the planarization layer, and the ground contact is within the opening in both the patterned bank layer and the planarization layer, and is in electrical contact with the ground line.
- The display panel of claim 3, wherein each LED is bonded to a corresponding bottom electrode with an In - Au compound.
- The display panel of claim 3, wherein the one or more top electrode layers comprises a transparent conductive oxide.
- The display panel of claim 18, wherein the transparent conductive oxide is indium-tin oxide.
- The display panel of claim 3, wherein the one or more top electrode layers comprises a transparent conductive polymer.
Description
1. Field
Embodiments of the present invention relate to display systems. More particularly embodiments of the present invention relate to a grounding structure for an active matrix display panel.
2. Background Information
Flat panel displays are gaining popularity in a wide range of electronic devices. Common types of flat panel displays include active matrix displays and passive matrix displays. Each pixel in an active matrix display panel is driven by active driving circuitry, while each pixel in a passive matrix display panel does not use such driving circuitry. High-resolution color display panels, such as modern computer displays, smart phones and televisions typically use an active matrix display panel structure for better image quality.
One kind of display panel that is finding commercial application is an active matrix organic light emitting diode (AMOLED) display panel. FIG. 1 is a top view illustration of a top emission AMOLED display panel. FIG. 2 is a cross-sectional side view illustration of FIG. 1 taken along line X-X in the pixel area 104 and line Y-Y crossing the ground ring 116 in the non-pixel area. The AMOLED display panel 100 illustrated in FIGS. 1-2 generally includes a thin film transistor (TFT) substrate 102 supporting a pixel area 104 and non-pixel area outside of the pixel area 102. A TFT substrate 102 is also referred to as a backplane. A TFT substrate which has been further processed to additionally include the pixel area and non-pixel area is also often referred to as a backplane.
Citations (137)
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Record as JSON
{
"publication_number": "US9343448B2",
"country": "US",
"kind": "B2",
"title": "Active matrix emissive micro LED display",
"abstract": "A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.",
"claims": [
"1. A display panel comprising: a lower conductive layer including a ground line; a planarization layer over the lower conductive layer; an opening in the planarization layer; a patterned top conductive layer over the planarization layer, wherein the patterned top conductive layer includes: an array of bottom electrodes; and a ground contact within the opening in the planarization layer and in electrical contact with the ground line; a corresponding plurality of light emitting diodes (LEDs) bonded to the array of bottom electrodes; and one or more top electrode layers on and in electrical contact with the plurality of LEDs and the ground contact.",
"2. The display panel of claim 1, wherein each LED comprises an inorganic semiconductor-based p-n diode.",
"3. The display panel of claim 2, wherein each LED is a vertical LED with a maximum width of 1 μm-100 μm.",
"4. The display panel of claim 3, wherein each bottom electrode is independently addressable.",
"5. The display panel of claim 4, wherein each LED device has a maximum width of 1 μm-20 μm.",
"6. The display panel of claim 3, wherein the one or more top electrode layers includes a single top electrode layer on and in electrical contact with the plurality of LEDs and the ground contact.",
"7. The display panel of claim 3, wherein the one or more top electrode layers includes a plurality of top electrode layers.",
"8. The display panel of claim 7, wherein each top electrode layer spans over a plurality of rows of LEDs.",
"9. The display panel of claim 7, wherein each top electrode layer spans over a single row of LEDs.",
"10. The display panel of claim 3, further comprising a patterned bank layer including an array of bank openings over the planarization layer, wherein each LED is within a corresponding bank opening.",
"11. The display panel of claim 10, further comprising a passivation layer spanning sidewalls of the array of LEDs within the array of bank openings, wherein the passivation layer does not completely cover a top conductive contact of each LED.",
"12. The display panel of claim 11, wherein the one or more top electrode layers spans across the passivation layer.",
"13. The display panel of calm 11, wherein the passivation layer is transparent to the visible wavelength spectrum.",
"14. The display panel of claim 11, wherein the patterned bank layer is opaque.",
"15. The display panel of claim 11, wherein the passivation layer spans a quantum well structure for each LED.",
"16. The display panel of claim 11, wherein the opening is formed in the patterned bank layer and the planarization layer, and the ground contact is within the opening in both the patterned bank layer and the planarization layer, and is in electrical contact with the ground line.",
"17. The display panel of claim 3, wherein each LED is bonded to a corresponding bottom electrode with an In - Au compound.",
"18. The display panel of claim 3, wherein the one or more top electrode layers comprises a transparent conductive oxide.",
"19. The display panel of claim 18, wherein the transparent conductive oxide is indium-tin oxide.",
"20. The display panel of claim 3, wherein the one or more top electrode layers comprises a transparent conductive polymer."
],
"description_excerpt": "1. Field\n\nEmbodiments of the present invention relate to display systems. More particularly embodiments of the present invention relate to a grounding structure for an active matrix display panel.\n\n2. Background Information\n\nFlat panel displays are gaining popularity in a wide range of electronic devices. Common types of flat panel displays include active matrix displays and passive matrix displays. Each pixel in an active matrix display panel is driven by active driving circuitry, while each pixel in a passive matrix display panel does not use such driving circuitry. High-resolution color display panels, such as modern computer displays, smart phones and televisions typically use an active matrix display panel structure for better image quality.\n\nOne kind of display panel that is finding commercial application is an active matrix organic light emitting diode (AMOLED) display panel. FIG. 1 is a top view illustration of a top emission AMOLED display panel. FIG. 2 is a cross-sectional side view illustration of FIG. 1 taken along line X-X in the pixel area 104 and line Y-Y crossing the ground ring 116 in the non-pixel area. The AMOLED display panel 100 illustrated in FIGS. 1-2 generally includes a thin film transistor (TFT) substrate 102 supporting a pixel area 104 and non-pixel area outside of the pixel area 102. A TFT substrate 102 is also referred to as a backplane. A TFT substrate which has been further processed to additionally include the pixel area and non-pixel area is also often referred to as a backplane.",
"cpc": [
"H10W 72/0198",
"H01L 25/167",
"H01L 33/06",
"H01L 33/38",
"H01L 33/42",
"H01L 33/54",
"H01L 33/62",
"H10D 86/40",
"H10D 86/60",
"H10H 20/812",
"H10H 20/831",
"H10H 20/833",
"H10H 20/853",
"H10H 20/857",
"H10W 70/093",
"H10W 70/099",
"H10W 70/60",
"H10W 72/0711",
"H10W 72/07141",
"H10W 72/07178",
"H10W 72/073",
"H10W 72/07336",
"H10W 72/352",
"H10W 72/874",
"H10W 90/00"
],
"ipc": [
"H01L 25/16",
"H01L 33/06",
"H01L 33/38",
"H01L 33/42",
"H01L 33/54",
"H01L 33/62"
],
"assignees": [
"LuxVue Technology Corp"
],
"inventors": [
"Kapil V. Sakariya",
"Andreas Bibl",
"Hsin-Hua Hu"
],
"filing_date": "2015-09-21",
"publication_date": "2016-05-17",
"grant_date": "2016-05-17",
"priority_date": "2012-12-10",
"application_number": "US-201514860185-A",
"family_id": "50879993",
"cited_by_count": 33,
"citations": [
"US6403985B1",
"JPH0845972A",
"US5592358A",
"US5996218A",
"US5851664A",
"US5839187A",
"US5888847A",
"US6670038B2",
"WO1998048319A1",
"US6878607B2",
"US6521511B1",
"US6629553B2",
"US5903428A",
"JP3406207B2",
"US6531996B1",
"US6420242B1",
"US6071795A",
"US20010029088A1",
"US6335263B1",
"US6558109B2",
"US7880184B2",
"US7888690B2",
"US6613610B2",
"US7358158B2",
"US20020076848A1",
"US20090284501A1",
"US20020158835A1",
"US7723764B2",
"US7148127B2",
"US7160633B2",
"US20030017360A1",
"WO2003012884A1",
"US20030094615A1",
"US20030177633A1",
"US7033842B2",
"US7928465B2",
"US6911666B2",
"US7208337B2",
"US7585703B2",
"US6786390B2",
"US20040217704A1",
"US7353596B2",
"US7797820B2",
"US20080163481A1",
"JP2004303706A",
"US20040208210A1",
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"US20060169993A1",
"US20060202210A1",
"US20060208271A1",
"US20060238463A1",
"US20120168776A1",
"US8497512B2",
"US7994711B2",
"JP2007173408A",
"US7795804B2",
"US20130234115A1",
"US20110057866A1",
"US7910945B2",
"US7791267B2",
"US7884543B2",
"US20080093606A1",
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"US7999454B2",
"US20100051910A1",
"KR101051488B1",
"US20100188794A1",
"KR20100089115A",
"US20100193822A1",
"US8023248B2",
"US20100248484A1",
"US20100270567A1",
"US20100295078A1",
"US20110003410A1",
"US20110068674A1",
"US20110084291A1",
"US20110114969A1",
"US20120223875A1",
"US20110169429A1",
"US20110198598A1",
"WO2011102030A1",
"WO2011123285A1",
"US20110291151A1",
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"US20120146030A1",
"US20120168714A1",
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"US20130210194A1",
"US20130285086A1",
"US20140027709A1",
"US20140084482A1",
"US20140084240A1",
"US20140159064A1"
]
}
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