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Shallow trench isolation

Term · Semiconductors · MLC-T-SEM-000306

A technique used in semiconductor manufacturing to electrically isolate active device regions on an integrated circuit. Trenches are etched into the silicon substrate, filled with an insulating dielectric material like silicon dioxide, and then planarized. This method provides superior isolation compared to older local oxidation of silicon (LOCOS) techniques.

Table 1. Record
IdentifierMLC-T-SEM-000306
FieldSemiconductors
SubjectFront-End Process
AbbreviationSTI
Record as JSON 
{
  "id": "MLC-T-SEM-000306",
  "term": "Shallow trench isolation",
  "field": "Semiconductors",
  "definition": "A technique used in semiconductor manufacturing to electrically isolate active device regions on an integrated circuit. Trenches are etched into the silicon substrate, filled with an insulating dielectric material like silicon dioxide, and then planarized. This method provides superior isolation compared to older local oxidation of silicon (LOCOS) techniques.",
  "abbreviation": "STI",
  "subject": "Front-End Process",
  "url": "https://mlchart.com/terminology/semiconductors/shallow-trench-isolation/"
}

Record 318 of 390 in Semiconductors terminology (MLC-0108). Request the full dataset.