Wet bottling process for small diameter deep trench capacitors

{
  "publication_number": "US2016163711A1",
  "country": "US",
  "kind": "A1",
  "title": "Wet bottling process for small diameter deep trench capacitors",
  "abstract": "A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, masking only a top surface of the SOI layer and a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material without masking any surface of the base substrate exposed within a lower portion of the deep trench, and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer.",
  "claims": [
    "1. A method comprising: forming a deep trench in a semiconductor-on-insulator substrate comprising an SOI layer directly on top of a buried oxide layer directly on top of a base substrate; masking a top surface of the SOI layer and an entirety of a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material, wherein a bottommost surface of the dielectric material in the deep trench is located above an interface between the buried oxide layer and the base substrate; and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer. 2. The method of claim 1, wherein forming the bottle shaped trench is performed sequentially following masking only the top surface and the sidewall of the SOI layer with the dielectric material. 3. The method of claim 1, wherein the deep trench comprises an aspect ratio of 50:1 in which a depth is 50 times larger than a diameter or a width of the upper portion of the deep trench. 4. The method of claim 1, wherein the deep trench comprises a width or diameter less than about 55 nm. 5. The method of claim 1, further comprising: forming a buried capacitor plate in the base substrate by introducing dopant through a sidewall and a bottom surface of the lower portion of the bottle shaped trench; forming a node dielectric by conformally depositing a dielectric material along an entire sidewall of the bottle shaped trench and the bottom surface of the bottle shaped trench; and forming an inner electrode directly on top of the node dielectric substantially filling the bottle shaped trench. 6. The method of claim 1, further comprising: forming a buried capacitor plate in the base substrate by introducing dopant of a second conductivity type through a sidewall and a bottom surface of the lower portion of the bottle shaped trench; forming a node dielectric by conformally depositing a dielectric material along an entire sidewall of the bottle shaped trench and the bottom surface of the bottle shaped trench; forming an inner electrode directly on top of the node dielectric substantially filling the bottle shaped trench; and forming a buried strap to electrically connect an inner electrode of the deep trench capacitor with a source region of a nearby transistor. 7. The method of claim 1, further comprising: forming a deep trench capacitor within the deep trench; and forming a buried strap to electrically connect an inner electrode of the deep trench capacitor with a source region of a nearby transistor. 8. A method comprising: forming a deep trench in a semiconductor-on-insulator substrate comprising an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, the deep trench comprising an upper portion aligned with the SOI layer and the buried oxide layer, and a lower portion aligned with the base substrate; depositing, anisotropically, a non-conformal dielectric layer directly on top of the semiconductor-on-insulator substrate using a high temperature high pressure CVD technique, the non-conformal dielectric layer covering an entirety of a sidewall of the SOI layer exposed in the deep trench, wherein a bottommost surface of the non-conformal dielectric layer in the deep trench is located above an interface between the buried oxide layer and the base substrate; and enlarging a diameter or width of the lower portion of the deep trench by etching the base substrate selective to the non-conformal dielectric layer and the buried oxide layer to form a bottle shaped trench. 9. The method of claim 8, wherein enlarging the diameter or width of the lower portion of the deep trench is performed sequentially following depositing the non-conformal dielectric layer, the non-conformal dielectric layer masking or protecting the SOI layer during enlarging of the diameter or width of the lower portion of the deep trench. 10. The method of claim 8, wherein a reaction time of the high temperature high pressure chemical vapor deposition technique used to deposit the non-conformal dielectric layer does not exceed 40 seconds. 11. The method of claim 8, wherein the deep trench comprises a width or diameter less than about 55 nm. 12. The method of claim 8, further comprising: forming a buried capacitor plate in the base substrate by introducing dopant through a sidewall and a bottom surface of the lower portion of the bottle shaped trench; forming a node dielectric by conformally depositing a dielectric material along an entire sidewall of the bottle shaped trench and the bottom surface of the bottle shaped trench; and forming an inner electrode directly on top of the node dielectric substantially filling the bottle shaped deep trench. 13. The method of claim 8, further comprising: forming a buried capacitor plate in the base substrate by introducing dopant of a second conductivity type through a sidewall and a bottom surface of the lower portion of the bottle shaped trench; forming a node dielectric by conformally depositing a dielectric material along an entire sidewall of the bottle shaped trench and the bottom surface of the bottle shaped trench; forming an inner electrode directly on top of the node dielectric substantially filling the bottle shaped trench; and forming a buried strap to electrically connect an inner electrode of the deep trench capacitor with a source region of a nearby transistor. 14. The method of claim 8, further comprising: forming a deep trench capacitor within the deep trench; and forming a buried strap to electrically connect an inner electrode of the deep trench capacitor with a source region of a nearby transistor. 15. A method comprising: forming a deep trench in a semiconductor-on-insulator substrate comprising an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, the deep trench comprising an upper portion aligned with the SOI layer and the buried oxide layer, and a lower portion aligned with the base substrate; depositing, anisotropically, a non-conformal dielectric layer directly on top of the semiconductor-on-insulator substrate using a high temperature high pressure chemical vapor deposition technique, wherein the high temperature high pressure chemical vapor deposition technique comprises a reaction temperature of at least 700° C., a pressure above atmospheric pressure, and a deposition reaction time no greater than 40 seconds, the non-conformal dielectric layer only covering an entirety of a sidewall of the SOI layer exposed in the deep trench, wherein a bottommost surface of the non-conformal dielectric layer in the deep trench is located above an interface between the buried oxide layer and the base substrate; and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the non-conformal dielectric layer and the buried oxide layer. 16. The method of claim 15, wherein forming the bottle shaped trench is performed sequentially following depositing the non-conformal dielectric layer, the non-conformal dielectric layer masking or protecting the SOI layer during forming of the bottle shaped trench. 17. The method of claim 15, wherein the deep trench comprises a width or diameter less than about 55 nm. 18. The method of claim 15, further comprising: forming a buried capacitor plate in the base substrate by introducing dopant through a sidewall and a bottom surface of the lower portion of the bottle shaped trench; forming a node dielectric by conformally depositing a dielectric material along an entire sidewall of the bottle shaped trench and the bottom surface of the bottle shaped trench; and forming an inner electrode directly on top of the node dielectric substantially filling the bottle shaped deep trench. 19. The method of claim 15, further comprising: forming a buried capacitor plate in the base substrate by introducing dopant of a second conductivity type through a sidewall and a bottom surface of the lower portion of the bottle shaped trench; forming a node dielectric by conformally depositing a dielectric material along an entire sidewall of the bottle shaped trench and the bottom surface of the bottle shaped trench; forming an inner electrode directly on top of the node dielectric substantially filling the bottle shaped trench; and forming a buried strap to electrically connect an inner electrode of the deep trench capacitor with a source region of a nearby transistor. 20. The method of claim 15, further comprising: forming a deep trench capacitor within the deep trench; and forming a buried strap to electrically connect an inner electrode of the deep trench capacitor with a source region of a nearby transistor."
  ],
  "description_excerpt": "The present invention relates generally to deep trench capacitors fabricated in a semiconductor substrate, and, more particularly, to a modified wet bottling process for small diameter deep trench capacitors.\n\nDeep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from about 4 fF (femto-Farad) to about 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.\n\nSemiconductor-on-insulator (SOI) devices formed on an SOI substrate or on a hybrid substrate provide high performance in advanced semiconductor chips. In SOI devices, the capacitive coupling between a substrate and semiconductor devices is reduced by the presence of a buried insulator layer. By forming a deep trench capacitor in the SOI substrate, SOI logic devices such as SOI transistors and deep trench capacitors may be formed on the same SOI substrate, thereby enabling embedding of deep trench capacitors into the SOI substrate that also contain high performance SOI logic devices. Such embedded deep trench capacitors enable various functionality including embedded dynamic access memory (eDRAM) and other embedded electronic components requiring a capacitor.",
  "cpc": [
    "H10D 1/047",
    "H01L 21/02271",
    "H01L 21/28",
    "H01L 21/30604",
    "H01L 21/84",
    "H01L 27/10867",
    "H01L 27/1087",
    "H01L 28/60",
    "H10B 12/0385",
    "H10B 12/0387",
    "H10B 12/373",
    "H10D 1/665",
    "H10D 86/01",
    "H10P 14/6334",
    "H10P 14/69215",
    "H10P 14/69433",
    "H10P 50/648",
    "H10P 50/693"
  ],
  "ipc": [
    "H01L 21/02",
    "H01L 21/28",
    "H01L 21/306",
    "H01L 21/84",
    "H01L 27/108",
    "H10N 97/00",
    "H01L 27/01"
  ],
  "assignees": [
    "International Business Machines Corp"
  ],
  "inventors": [
    "Russell H. Arndt",
    "Babar A. Khan",
    "Byeong Y. Kim",
    "Xinhui Wang"
  ],
  "filing_date": "2014-12-04",
  "publication_date": "2016-06-09",
  "priority_date": "2014-12-04",
  "application_number": "US-201414560203-A",
  "family_id": "56095022",
  "cited_by_count": 467
}