Mark formation method and device manufacturing method

{
  "publication_number": "US9568826B2",
  "country": "US",
  "kind": "B2",
  "title": "Mark formation method and device manufacturing method",
  "abstract": "A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is forced by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern.",
  "claims": [
    "1. A mark forming method comprising: forming, oil a substrate, an intermediate layer to which a polymer layer containing a block copolymer is adherable; removing a portion of the intermediate layer formed on the substrate; forming an alignment mark in an area of the substrate, the area being an area from which the portion of the intermediate layer has been removed; and forming a device pattern by applying the polymer layer containing the block copolymer on the intermediate layer, wherein the alignment mark is formed on the substrate not via the intermediate layer, and the polymer layer is formed on the substrate via the intermediate layer.",
    "2. The mark forming method according to claim 1, comprising: allowing the polymer layer to form a self-assembled area; selectively removing the polymer layer from a portion of the self-assembled area; and processing a device pattern formation area of a layer to be processed of the substrate via the portion of the self-assembled area from which the polymer layer has been selectively removed.",
    "3. The mark forming method according to claim 1, comprising removing a part of a portion, of the intermediate layer, located at a device pattern formation area of the substrate.",
    "4. A mark forming method comprising: exposing an image of a first mark on a mark formation layer of a substrate and forming, based on the image of the first mark, a second mark including projected line portion in an area of the substrate; applying a polymer layer containing a block copolymer on a certain portion of the area of the substrate, the area being an area in which the second mark has been formed, the certain portion being different from the projected line portion; allowing the polymer layer to form a self-assembly area; selectively removing the polymer layer from a portion of the self-assembly area; and processing the mark formation layer of the substrate using the self-assembly area from which the polymer layer has been selectively removed.",
    "5. The mark forming method according to claim 4, wherein the second mark includes a plurality of guide patterns which have a projected and linear shape and which are periodically formed in a first direction at a portion different from the projected line portion; applying the polymer layer on the certain portion is applying the polymer layer in a plurality of recessed portions located between the plurality of guide patterns; and allowing the polymer layer to form the self-assembly area is allowing the polymer layer in the plurality of recessed portions to form a self-assembled area having periodicity in the first direction.",
    "6. The mark forming method according to claim 5, wherein the second mark includes: a plurality of first line portions having a projected shape and arranged periodically in the first direction; a plurality of second line portions having a projected shape and arranged periodically in a second direction orthogonal to the first direction; a plurality of first guide patterns having a projected and linear shape and periodically formed in the first direction between two adjacent line portions of the plurality of projected first line portions; and a plurality of second guide patterns having a projected and linear shape and periodically formed in the second direction between two adjacent line portions of the plurality of projected second line portions.",
    "7. The mark forming method according to claim 6, wherein a period of the plurality of first guide patterns and a period of the plurality of second guide patterns are different.",
    "8. A method for producing a device comprising: forming, in a substrate, an alignment mark for alignment between layers to be formed on the substrate by using the mark forming method as defined in claim 1; performing the alignment by using the alignment mark and performing exposure for the substrate; and processing the exposed substrate.",
    "9. A method for producing a device comprising: forming, in a substrate, an alignment mark for alignment between layers to be formed on the substrate by using the mark forming method as defined in claim 4; performing the alignment by using the alignment mark and performing exposure for the substrate; and processing the exposed substrate."
  ],
  "description_excerpt": "The present invention relates to a mark forming method for forming a mark in a mark formation area of a substrate and a method for producing device using the mark forming method.\n\nA semiconductor device typically includes a plurality of layers of circuit patterns formed on a substrate, and an alignment mark for positioning or alignment is formed in a mark formation area of a predetermined layer of the substrate so as to accurately align the circuit patterns of the plurality of layers relative to each other, in a production step of the semiconductor device. In a case that the substrate is a semiconductor wafer (hereinafter referred to simply as “wafer”), the alignment mark is referred to also as a “wafer mark”.\n\nConventionally, the minutest circuit pattern of the semiconductor device is forced, for example, with a dry or liquid immersion lithography step using a dry or liquid immersion exposure apparatus of which exposure wavelength is 193 nm. It is expected that formation of a circuit pattern more minute, for example, than a 22 nm node is difficult even by combining the conventional photolithography and the double-patterning process which has been recently developed.\n\nIn view of this situation, it has been suggested using the directed self-assembly (directed self-organization) of a block copolymer between patterns formed by using the lithography step so as to generate a minute structure of nano-scale (sub-lithography structure), thereby forming a circuit pattern more minute than the resolution limit of the current lithography technique (see, fox example, the specification of U.S. Patent Application Publication No.",
  "cpc": [
    "H10P 50/695",
    "B82Y 40/00",
    "G03F 7/0002",
    "G03F 7/168",
    "G03F 7/20",
    "G03F 7/70341",
    "G03F 9/708",
    "H01L 21/02118",
    "H01L 21/0274",
    "H01L 2223/54426",
    "H01L 23/544",
    "H10P 14/683",
    "H10P 76/2041",
    "H10W 46/00",
    "H10W 46/301",
    "H10W 46/503"
  ],
  "ipc": [
    "G03F 7/16",
    "G03F 7/20",
    "H01L 23/544",
    "H10W 10/00"
  ],
  "assignees": [
    "Nikon Corp"
  ],
  "inventors": [
    "Tomoharu Fujiwara"
  ],
  "filing_date": "2015-01-06",
  "publication_date": "2017-02-14",
  "grant_date": "2017-02-14",
  "priority_date": "2012-07-10",
  "application_number": "US-201514590488-A",
  "family_id": "49916044",
  "cited_by_count": 1,
  "citations": [
    "US20030025890A1",
    "US20070242247A1",
    "US20100297847A1",
    "JP2010269304A",
    "US20120112370A1"
  ]
}